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first_img Samsung Electro-Mechanics proposed the direction of AI semiconductor substrate MLC integration

On September 10, Kim Sang-hoon, the head of the packaging division at Samsung Electro-Mechanics, delivered a speech at the KPCA Show International Seminar INSIGHT 2026 held at the Incheon Songdo Conference Center, proposing a multilayer core (MLC) technology direction to address the large-scale and high-multilayer challenges of AI semiconductor packaging substrates.Kim Sang-hoon stated that in the past, the single-layer core (SLC) method, which increased the thickness of a single CCL, led to increased difficulty in processing internal vias and circuits as the core thickened, and the size of the vias became limited. The MLC approach shifts to a combination of CCL and PPG multilayers, or even a mixed structure of two CCLs, which can simultaneously enhance rigidity and wiring freedom, while also allowing for ground or signal wiring to be arranged in the PPG layer. A bonding layer added between the two CCLs can provide more stable support for the substrate, but the process is more complex.Currently, the commonly used bump pitch in mass production is above 90μm, with around 85μm being the turning point for printed fine solder ball processes. The difficulty significantly increases around 80μm, and the 55-45μm range may shift towards metal bumps. Glass cores are another option, offering higher rigidity and lower thermal expansion coefficients, which help reduce warping in large packages, but issues related to fragility and micro-hole plating technology need to be addressed. The substrate must meet signal integrity, power integrity, and mechanical integrity requirements simultaneously, with high-performance packaging substrate layers expected to evolve from about 20 layers at the 90mm level to 120mm and even more than 40 layers.

first_img Samsung Electro-Mechanics and LG Innotek advance Intel's EMIB-T substrate supply

According to a report by ZDNet Korea on the 9th, Samsung Electro-Mechanics and LG Innotek are advancing into the Intel EMIB-T packaging substrate supply chain, with related product development and testing already underway. EMIB connects chips with small silicon bridges, which Intel previously used mainly for its own chips; the improved EMIB-T is expanding external sales. The next-generation AI accelerator TPU that Google plans to launch in the second half of next year will be the first to use EMIB-T. EMIB-T inserts silicon vias for power transmission within the silicon bridge.Insiders say that Samsung Electro-Mechanics has developed EMIB substrate samples over the years and is currently advancing EMIB-T supply based on the 2.1D packaging substrate concept. Recently, LG Innotek delivered EMIB-T packaging substrates to SK Hynix for sample testing, and both parties are installing HBM on the substrate to evaluate product characteristics.Currently, EMIB-T packaging substrates are supplied by Japan's Ibiden, Shinkawa Electric, Taiwan's Xinxing Electronics, and Austria's AT&S. Ibiden has decided to utilize idle factories to construct a dedicated production line for Intel's EMIB-T substrates, with an investment scale of about 20 trillion Korean won, and it is reported that they have already received advance payments from Google, Amazon, Intel, and others.

first_img Samsung's 4-nanometer production capacity is more than half used for HBM4 substrate chips

Samsung Electronics' wafer foundry division has recently surpassed 50% in the allocation of production capacity for the sixth-generation high bandwidth memory HBM4 substrate chips in the 4-nanometer process. The industry states that this division will invest more than half of its 4-nanometer wafers into HBM4 substrate chip manufacturing in the second half of this year to expand supply to companies like NVIDIA, Broadcom, and AMD.Samsung initiated mass production and shipment of HBM4 in February this year and plans to increase supply starting from the third quarter, significantly increasing the related wafer input since mid-year. This chip is based on Samsung's wafer foundry 4-nanometer (SF4) process. As of last month, over 50% of its total 4-nanometer capacity has been allocated to HBM4 substrate chips. According to insiders, Samsung's 4-nanometer process is currently at full capacity, with HBM4 substrate chips accounting for about 50% to 60%, and this high proportion will be maintained in the second half of the year.Samsung's wafer foundry production lines at Pyeongtaek Plant 2 and Plant 3 are mass-producing processes ranging from 4 to 7 nanometers, with a monthly capacity of about 30,000 wafers for the 4-nanometer process. Based on this, the wafer input related to HBM4 substrate chips is estimated to be about 15,000 wafers per month. During the second quarter earnings call, Samsung stated that it expects HBM4 revenue to increase more than threefold quarter-over-quarter in the third quarter, with HBM4 revenue in the second half expected to exceed 60% of the company's overall HBM revenue.
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