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first_img Micron grants the highest bonuses in history, and the Taiwan union states it will continue to push for strikes

Micron announced today that it will distribute 2026 fiscal year bonuses to over 60,000 employees worldwide to acknowledge the company's achievements this year, marking the highest bonuses in Micron's history. Taiwan is a key hub for Micron's global technology leadership, with approximately 15,000 employees and a cumulative investment of over NT$1.6 trillion.In Taiwan, the 2026 fiscal year bonuses include a NT$1 million cash bonus for each employee who joins before August 29, 2025, with subsequent hires receiving bonuses proportionate to their duration of employment; an annual performance bonus that can reach up to 500% of the basic target; and additional stock awards. Production line employees in Taiwan will receive total compensation equivalent to 35 to 68 months of salary. The cash compensation for Micron's employees in Taiwan for the 2026 fiscal year will start at NT$1.7 million; entry-level engineers will have an average cash compensation of NT$2.9 million, with an average total compensation of NT$3.4 million after including stock awards calculated at grant value. The annual performance adjustment stock awards will cover 100%.Regarding Micron's announcement without reaching a consensus with the union, the union stated after collecting member opinions: grassroots members demand institutional reform and equal negotiation, calling for a change in the IPP profit-sharing system to a 15% profit-sharing system, stating that one-time bonuses cannot resolve the issue, and expressing the hope to establish a calculation basis directly linked to the company's actual profits. If there is no response, the union will continue to move towards a strike. The Ministry of Labor stated that it has fully grasped the relevant information and is maintaining close contact with the Taoyuan City Government, the Central Taiwan Science Park Administration, and the Taichung City Government.

first_img Micron plans to expand HBM production capacity to approximately 100,000 wafers per month by the end of the year

According to Electronic News on September 3, Micron plans to double its high bandwidth memory (HBM) production capacity compared to last year, with a maximum addition of 60,000 wafers per month by the end of this year. Insiders say that Micron's HBM output was about 40,000 to 50,000 wafers per month last year, and it is expected to reach about 100,000 wafers per month by the end of the year, narrowing the gap with Samsung Electronics and SK Hynix.Micron is increasing procurement orders from multiple HBM equipment suppliers, with production bases mainly in Taiwan and Singapore, continuously introducing equipment. Currently, the output is mainly HBM3E 12-layer, with HBM4 12-layer accounting for about 20% to 30% at the beginning of this year, which may rise to as high as 50% by the end of the year. HBM4 12-layer will be used in NVIDIA's latest AI accelerator, Vera Rubin, and Micron has started mass production of this product since the second quarter of this year.Micron CEO Mehrotra stated in the Q3 earnings call for fiscal year 2026 in June this year that the ramp-up speed of HBM4 12-layer mass production is about twice that of HBM3E 12-layer, and cumulative revenue from HBM4 shipments has exceeded $1 billion. The industry believes that Samsung and SK Hynix each have HBM production capacities of about 150,000 to 200,000 wafers per month. Counterpoint data shows that in Q2 of this year, the global HBM market shares were SK Hynix 50%, Samsung 32%, and Micron 18%. Micron is also preparing related investments in Hiroshima, Japan.

first_img TSMC temporarily uses micro-bump packaging for HBM and requires the development of a 5μm solution

According to sources in the materials industry, on September 2, TSMC is expected to continue using traditional micro-bump technology rather than hybrid bonding in the short term for connecting high-bandwidth memory (HBM) with AI accelerators in advanced packaging. Considering the development cycle of related materials, finer pitch micro-bumps are expected to be used until the later stages of HBM4 and the early stages of HBM5. TSMC has requested its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micron bumps, with suppliers from South Korea and Japan beginning development, and mass production of 5μm bumps expected to start in the second half of 2028.Currently, the bump height of the third-generation extended HBM, namely HBM3E, is about 15-25μm, while HBM4 is close to about 10μm. Japanese material suppliers have previously stated that it is difficult to guarantee quality below 15μm. The reduction and refinement of bumps are due to the height limitations of HBM cubes and the demand for higher interconnection density. JEDEC specifies that the maximum height for HBM stacks is 775μm. In TSMC's advanced CoWoS packaging, the HBM stacks assembled by GPU and memory suppliers are mounted onto the silicon interposer via micro-bumps, with the 16-layer DRAM chip stacks completed within HBM packaging by SK hynix and Samsung Electronics.The first and second generations of HBM used larger solder bumps, while micro-bumps became mainstream around the HBM3 generation. SK hynix uses the MR-MUF process, while Samsung Electronics uses TC-NCF. Hybrid bonding allows for thinner and denser interconnections through direct bonding of copper pads; TSMC has utilized this on its SoIC platform for logic chip stacking, but HBM still connects to the interposer using micro-bumps.

hot_img Micron will issue the highest performance bonuses in history to avoid worker strikes

According to Reuters, Micron Technology's unions in Taoyuan and Taichung, Taiwan are preparing for a strike. The union claims to represent nearly 10,000 of Micron's approximately 15,000 employees in the two locations, and an internal survey shows that over 80% of members support the strike. The core of the labor dispute revolves around bonus distribution— the union believes that the current incentive plan does not adequately reflect the company's profitability and is demanding a one-time additional bonus for this fiscal year, as well as a shift to quarterly profit sharing of 15% of operating profits starting from the 2027 fiscal year. Micron previously responded that it would issue the highest performance bonuses in history, but the union believes the company has not adequately explained the performance calculation method, and it seems to be more closely tied to revenue rather than profit.As the world's third-largest memory chip manufacturer, Micron reported revenue of $41.46 billion and a net profit of $28.24 billion in the third fiscal quarter, with a market capitalization of approximately $1.1 trillion. Taiwan is Micron's largest manufacturing base, with a cumulative investment of NT$1.4 trillion, producing DRAM and HBM. If the strike proceeds, it may impact the global memory chip supply. The Taichung Science Park Administration stated that it is closely monitoring the situation and has prepared a labor mediation mechanism. Previously, the Samsung union also raised similar profit-sharing demands and obtained a special bonus pool of 10.5% of the chip division's operating profits after negotiations.

first_img Micron warns that AI storage walls are intensifying, with HBM accounting for about 17% of the interruptions in Meta Llama 3 training

According to TrendForce, at Hot Chips 2026, Micron emphasized that the progress of AI computing power is faster than storage improvements, and the challenge of the "storage wall" is becoming increasingly prominent. Micron Fellow Raghu Sriramaneni pointed out that the computing power of AI accelerators increases approximately threefold every two years, while the bandwidth of HBM increases by less than double during the same period, and the gap may further widen. The deepening reliance on HBM also brings reliability issues; Micron cited Meta Llama 3 data indicating that HBM failures account for about 17% of unexpected training interruptions. New designs that blur the boundaries between computing and storage may help break through the bottleneck.The expansion of HBM also brings area and supply pressures: the latest generation of packaging integrates two GPUs with eight 12-layer HBM4 stacks, with storage accounting for about 90% of the semiconductor area, more than eight times the area occupied by GPUs; achieving equivalent capacity with HBM requires about three times the wafers of standard DDR5 DRAM. Thermal management has also become a key constraint, with solutions such as liquid cooling and ultra-thin chips being explored.Micron is advancing innovations in interconnect, packaging, and cooling, including SerDes and die-to-die PHY optimized for storage, larger size SiP and advanced packaging with glass substrates, as well as liquid cooling and hybrid bonding, and is developing fusion bonding to reduce thermal resistance and enhance data throughput.
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