hbm

KB Securities released a report on September 11, indicating that Samsung Electronics' HBM market share is expected to increase from 33% in the second quarter to 40% in the fourth quarter, mainly due to HBM4 sales in the third quarter growing more than three times quarter-on-quarter, and HBM4 is expected to account for over 60% of its total HBM sales in the second half of the year.Samsung Electronics has established comprehensive mass production of HBM4, supplied HBM4E samples to core customers, adopted the HBM5 architecture with 1c core bare chips and 2-nanometer base bare chips, and outlined the roadmap for the next-generation ZHBM. In terms of its foundry business, the 4-nanometer yield has stabilized above 80%, and the 2-nanometer GAA yield has rapidly increased to over 70%. KB Securities analyst Kim Dong-Won stated that the foundry business is expected to turn profitable starting in the third quarter, and the 2-nanometer yield may help it secure orders from major U.S. clients within the year.

According to a Reuters exclusive report on September 10, Chinese AI chip manufacturers have significantly raised prices due to a shortage of high-bandwidth memory. Huawei has raised the indicated price of the Ascend 950DT accelerator card to over 250,000 yuan, an increase of 20% to 50% compared to two months ago. Cambricon has raised the indicated price of its planned 690 chip by 20% to 30%, and both Muxi and Tian Shu Zhi Xin have also implemented similar price increases.The report states that the reasons include U.S. export controls and the high costs of high-bandwidth memory supplies in the gray market. Prices for earlier Huawei products such as the Ascend 950PR and 910C have also increased by about 30%. These price increases have raised the construction costs of AI computing power in China. Huawei, Cambricon, and other companies did not comment.

According to industry news, NVIDIA is considering adjusting the high bandwidth memory solution for the next-generation Rubin Ultra artificial intelligence accelerator from a 12-layer stack to an 8-layer stack.Against the backdrop of rising storage costs, NVIDIA is placing greater emphasis on unit bandwidth costs and overall system economics.

According to the Chosun Ilbo, China's largest DRAM manufacturer Changxin Memory Technologies (CXMT) has launched trial production of the fourth-generation high bandwidth memory HBM3, with initial yield stagnating at 25%, about one-third of the golden mass production yield of 80%. SK Hynix has been mass producing similar products since 2022, with a yield exceeding 90%.The front-end yield of Changxin Memory's HBM3 8-layer stacked products is about 30%, while the back-end yield is approximately 70%, resulting in final good products. The company supplies a small number of samples to Chinese companies such as Alibaba's Pingtouge and Cambricon, and continues to improve yields. Its G4 (17-nanometer) process ordinary DRAM has no major issues, but the DRAM chips used for HBM have larger areas and stricter electrical specifications.The industry attributes the reasons to the insufficient maturity of Through-Silicon Via (TSV) technology. Nomad Semi's analysis shows that Samsung's HBM2 has over 5,000 TSVs per chip, SK Hynix's HBM3 has over 8,000, while Changxin Memory has about 3,000. There is a gap of 4 to 5 years compared to Samsung and SK Hynix.

KB Securities warned that the inventory of memory semiconductors at Samsung Electronics and SK Hynix has fallen to less than 10 days of supply, and the available supply next year will be significantly insufficient. The agency reported on Monday that investment in artificial intelligence infrastructure is expanding at an unprecedented pace, leading to a severe supply shortage in the memory chip market. A key factor is the transition to HBM4, which requires about three times the wafers of traditional DRAM, and limited wafer capacity will reduce the available capacity of traditional DRAM.KB Securities expects that next year, the demand for DRAM and NAND will exceed supply by more than 10 percentage points. Research director Kim Dong-won stated that artificial intelligence servers will consume HBM, server DDR5, and enterprise-grade solid-state drives, potentially leading to a historic shortage. Global hyperscale data center operators have raised their expectations for artificial intelligence infrastructure investment next year to $1.3 trillion, a 60% increase from the previous year. The agency anticipates that memory semiconductors will account for 57% of total investment in artificial intelligence infrastructure next year, up from 14% last year, with TrendForce estimating this ratio could reach as high as 68%. Samsung Electronics' stock price has dropped nearly 28% from its peak, while SK Hynix has fallen nearly 40%.

According to TrendForce's latest research on the memory industry, in the second quarter of 2026, due to a significant increase in the contract price of Conventional DRAM, the overall revenue of the DRAM industry is expected to grow by 59.5% quarter-on-quarter, reaching nearly 154.73 billion USD.With the training of LLM models and AI inference stimulating the demand for AI Servers, shipments of HBM3e, LPDDR5X, and high-capacity RDIMMs are growing simultaneously, while Agentic AI applications are driving the demand for RDIMMs of various capacities. On the supply side, manufacturers' inventories are at a low point, and new supply is prioritized for Server applications, leading to a slight growth in overall DRAM bit shipments in the second quarter.

Samsung Electronics' wafer foundry division has recently surpassed 50% in the allocation of production capacity for the sixth-generation high bandwidth memory HBM4 substrate chips in the 4-nanometer process. The industry states that this division will invest more than half of its 4-nanometer wafers into HBM4 substrate chip manufacturing in the second half of this year to expand supply to companies like NVIDIA, Broadcom, and AMD.Samsung initiated mass production and shipment of HBM4 in February this year and plans to increase supply starting from the third quarter, significantly increasing the related wafer input since mid-year. This chip is based on Samsung's wafer foundry 4-nanometer (SF4) process. As of last month, over 50% of its total 4-nanometer capacity has been allocated to HBM4 substrate chips. According to insiders, Samsung's 4-nanometer process is currently at full capacity, with HBM4 substrate chips accounting for about 50% to 60%, and this high proportion will be maintained in the second half of the year.Samsung's wafer foundry production lines at Pyeongtaek Plant 2 and Plant 3 are mass-producing processes ranging from 4 to 7 nanometers, with a monthly capacity of about 30,000 wafers for the 4-nanometer process. Based on this, the wafer input related to HBM4 substrate chips is estimated to be about 15,000 wafers per month. During the second quarter earnings call, Samsung stated that it expects HBM4 revenue to increase more than threefold quarter-over-quarter in the third quarter, with HBM4 revenue in the second half expected to exceed 60% of the company's overall HBM revenue.

Future Asset Securities analyst Kim Young-gun stated that the expansion of Samsung Electronics' HBM shipments for AI applications is expected to offset the impact of the slowdown in growth of general-purpose memory chips next year. It is anticipated that Samsung Electronics' HBM shipment capacity and average selling price will soar by 57% and 49% respectively by 2027, expected to surpass the projected growth rates of 16% and 20% for general-purpose memory chips.Future Asset expects Samsung's earnings to be weighed down by the strengthening of the Korean won against the US dollar, but overall, it will remain robust. The agency has lowered its operating profit forecast for Samsung in 2026 by 5.7% to 370.057 trillion won and reduced it by 4.2% to 535.682 trillion won for 2027.

Researcher Schulz_Research stated that China's storage advancement is no longer a story of a single company, but rather a division of labor among three companies: CXMT is responsible for DRAM wafers, YMTC is responsible for NAND and has added DRAM in its latest factory, and the foundry controlled by YMTC, XMC, is responsible for stacking products from both. This division corresponds to the rules set by Beijing since late December last year, which state that new factory approvals must show that at least half of the equipment is domestically sourced, with exemptions only granted when there are no domestic options available. YMTC's Wuhan Phase III is the first advanced storage project to pass this rule and is set to begin production later this year.CXMT operates three 300mm DRAM factories, each producing about 100,000 wafers per month; models indicate it will reach 350,000 wafers by the end of 2026, and if all announced projects are completed, the total will exceed 600,000 wafers. YMTC's first two factories in Wuhan have a combined capacity of 200,000 wafers, with Phase III expected to reach 50,000 wafers by 2027 and full production of 100,000 wafers, along with plans to build two more factories of similar scale. XMC has two 12-inch factories, each with about 30,000 wafers, and an HBM packaging line producing about 3,000 wafers per month. China supplies about 10% of the global DRAM bits, with YMTC accounting for 14% of NAND bit shipments in the second quarter, and China consumes about 30% of global storage.CXMT has begun mass production of DDR5 and LPDDR5 and plans to start mass production of HBM3 this year, having already sent samples to domestic AI hardware developers. XMC has spent two years building HBM packaging based on hybrid bonding and YMTC's stacking IP, and is still advancing TSV technology.

According to the Chosun Ilbo report on September 7, SK Hynix is accelerating the increase of the production share of 10-nanometer sixth-generation (1c) DRAM. Industry data shows that its 1c DRAM share rose from about 10% in the first quarter of this year to about 13% in the second quarter, and is expected to reach about 24% in the third quarter and about 34% in the fourth quarter; it may rise to about 35% in the first quarter of next year, surpassing 1b (about 33%) for the first time and becoming the main process. The share of 1b (10-nanometer fifth-generation) DRAM peaked at about 43% in the second quarter of this year and has since begun to decline.By the end of the second quarter, Samsung Electronics had a 1c share of about 16% and Micron about 19%, both higher than SK Hynix's approximately 13%. Reports indicate that SK Hynix is accelerating the transition in the second half of the year, and in the fourth quarter, it may exceed Samsung Electronics' approximately 31% with about 34%. SK Hynix stated in its second-quarter earnings call that the supply of DRAM using the 1c process will substantially begin from the second quarter, and in the second half of the year, with the ramp-up of HBM4 and increased shipments of 1c general DRAM, the bit growth rate will be higher than in the first half.Samsung Electronics will use 1c DRAM starting with HBM4, with a running speed of about 11.7Gbps; SK Hynix previously prioritized ensuring mass production stability with verified 1b DRAM and advanced MR-MUF packaging, and will use 1c DRAM for the first time as the core chip for HBM starting with the next generation HBM4E. Counterpoint Research and others estimate that this year, the market share of HBM4 under the combined metrics of Nvidia, Google, and AMD is approximately 50% for SK Hynix in the mid-range, 20% for Samsung Electronics in the later range, and 10% for Micron in the later range.

According to Electronic News on September 3, Micron plans to double its high bandwidth memory (HBM) production capacity compared to last year, with a maximum addition of 60,000 wafers per month by the end of this year. Insiders say that Micron's HBM output was about 40,000 to 50,000 wafers per month last year, and it is expected to reach about 100,000 wafers per month by the end of the year, narrowing the gap with Samsung Electronics and SK Hynix.Micron is increasing procurement orders from multiple HBM equipment suppliers, with production bases mainly in Taiwan and Singapore, continuously introducing equipment. Currently, the output is mainly HBM3E 12-layer, with HBM4 12-layer accounting for about 20% to 30% at the beginning of this year, which may rise to as high as 50% by the end of the year. HBM4 12-layer will be used in NVIDIA's latest AI accelerator, Vera Rubin, and Micron has started mass production of this product since the second quarter of this year.Micron CEO Mehrotra stated in the Q3 earnings call for fiscal year 2026 in June this year that the ramp-up speed of HBM4 12-layer mass production is about twice that of HBM3E 12-layer, and cumulative revenue from HBM4 shipments has exceeded $1 billion. The industry believes that Samsung and SK Hynix each have HBM production capacities of about 150,000 to 200,000 wafers per month. Counterpoint data shows that in Q2 of this year, the global HBM market shares were SK Hynix 50%, Samsung 32%, and Micron 18%. Micron is also preparing related investments in Hiroshima, Japan.

According to sources in the materials industry, on September 2, TSMC is expected to continue using traditional micro-bump technology rather than hybrid bonding in the short term for connecting high-bandwidth memory (HBM) with AI accelerators in advanced packaging. Considering the development cycle of related materials, finer pitch micro-bumps are expected to be used until the later stages of HBM4 and the early stages of HBM5. TSMC has requested its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micron bumps, with suppliers from South Korea and Japan beginning development, and mass production of 5μm bumps expected to start in the second half of 2028.Currently, the bump height of the third-generation extended HBM, namely HBM3E, is about 15-25μm, while HBM4 is close to about 10μm. Japanese material suppliers have previously stated that it is difficult to guarantee quality below 15μm. The reduction and refinement of bumps are due to the height limitations of HBM cubes and the demand for higher interconnection density. JEDEC specifies that the maximum height for HBM stacks is 775μm. In TSMC's advanced CoWoS packaging, the HBM stacks assembled by GPU and memory suppliers are mounted onto the silicon interposer via micro-bumps, with the 16-layer DRAM chip stacks completed within HBM packaging by SK hynix and Samsung Electronics.The first and second generations of HBM used larger solder bumps, while micro-bumps became mainstream around the HBM3 generation. SK hynix uses the MR-MUF process, while Samsung Electronics uses TC-NCF. Hybrid bonding allows for thinner and denser interconnections through direct bonding of copper pads; TSMC has utilized this on its SoIC platform for logic chip stacking, but HBM still connects to the interposer using micro-bumps.

According to a report by South Korea's Seoul Economic Daily on August 31, the prices of HBM and DRAM used in AI accelerators continue to rise. Data from the Korea Trade Association shows that DRAM export volume decreased from approximately 681.7 million units in May to 591.74 million units in July, a decline of 13.2%. However, the export value increased from $11.428 billion to $13.552 billion, a growth of 18.5%, with the export unit price rising from $16.76 to $22.9, an increase of 36.6%.The supply of HBM4 to customers such as Nvidia is expanding, but the initial yield is lower than that of HBM3E, exacerbating the overall DRAM supply shortage. Samsung Electronics' memory division is reportedly planning to allocate about 70% of its capacity to long-term supply agreements until 2031, with major clients including Nvidia, Microsoft, and Google. Mega Grid Supply data shows that the spot price for HBM3E 36GB is $2,100, approximately 4 to 5 times the long-term contract price; the spot price for HBM4 16-layer, which is in mass production coordination, is about $3,500.The financial investment community expects Samsung Electronics' third-quarter revenue to reach 206.64 trillion won and operating profit to reach 116.38 trillion won, with operating profit expected to exceed 100 trillion won for the first time. SK Hynix's third-quarter revenue is expected to be 101.76 trillion won, with operating profit of 79.16 trillion won. Samsung Electronics is considering converting its only wafer foundry line S5 in the Pyeongtaek campus to memory production as early as next year.

According to South Korean media reports, Samsung Electronics is cooperating with Nvidia (NVDA.O) to develop 8-layer seventh-generation high bandwidth memory (HBM4E), significantly reducing the stacking height compared to the original plans of 12 layers and 16 layers. The speed specification proposed by Nvidia is 17-18Gbps, which is about 20% higher than Samsung's initial HBM4E sample speed of 14.4Gbps. This product is reported to be used for NVHBM.

According to Citrini analyst Jukan, SK Hynix is working on diversifying the foundry suppliers for the substrate chips used in high bandwidth memory (HBM), which are constructed by vertically stacking multiple memory chips. It is reported that the company is considering outsourcing part of the substrate chip production for the seventh generation HBM, namely HBM4E, to Intel's foundry. So far, SK Hynix has relied entirely on TSMC for outsourcing substrate chip production.This move is seen as an effort to establish a multi-supplier foundry strategy to reduce the concentration of the supply chain on TSMC while enhancing SK Hynix's bargaining power in pricing. According to industry insiders on August 31, SK Hynix is advancing a plan where the substrate chips for HBM4E may be jointly manufactured by TSMC and Intel, potentially starting from the HBM4E generation.As the market expects the cost burden of substrate chips for HBM4E to further increase. Since HBM products are mainly covered by long-term supply agreements (LTA), SK Hynix also finds it difficult to immediately pass on the higher foundry costs to customers by raising product prices. Therefore, industry observers believe that if Intel ultimately joins SK Hynix's substrate chip supply chain, the company will gain more options in terms of cost competitiveness and supply stability.

SemiAnalysis released the latest episode of its podcast, which pointed out that SK Hynix and Micron have been facing challenges in achieving the highest HBM4 speeds. In particular, SK Hynix had to redesign its base chip, resulting in delays in HBM4 deliveries to the NVIDIA Rubin platform.Samsung currently has the best HBM4 technology. Broadcom has traditionally relied heavily on Samsung for its HBM supply. Samsung's performance in the HBM3E generation was poor, which posed a disadvantage for Broadcom's ASICs. However, now Samsung is leading its competitors with HBM4, and this same supply chain relationship has become an advantage for Jalapeño.

According to reports from Seoul Economic Daily, Samsung Electronics is developing HBM4E (seventh generation) 8-layer products that meet NVIDIA's requirements, aiming to secure its position as a core partner in the supply of customized high-bandwidth memory NVHBM. This product reduces the stacking height compared to the originally planned 12-layer and 16-layer designs. The speed specifications proposed by NVIDIA are 17-18Gbps, which is about 20% higher than the speed of Samsung's initial HBM4E samples (14.4Gbps), and will be used for NVIDIA's publicly disclosed NVLink optimized specifications for NVHBM.The use of 8 layers, contrary to the previous logic of increasing capacity by adding more stacking layers in HBM, can reduce the difficulty of post-processing and yield pressure, which is beneficial for expanding supply and is seen as NVIDIA's strategy to alleviate memory shortages. NVHBM is expected to be applied starting with the next-generation AI GPU "Rubin Ultra," which is set to launch next year. This GPU will expand the interconnection scale between GPUs from a maximum of 72 to 576, enhancing overall computing power through hundreds of GPUs equipped with faster HBM.In the customized HBM market, Samsung is more competitive compared to SK Hynix and Micron, as NVHBM requires DRAM and the production capabilities of logic chip-based bare die designs, which Samsung can integrate. Industry insiders say that Samsung has verified the highest speed levels in HBM4, which can provide an advantage in speed competition.

SK Hynix CEO Kwak Noh-Jung stated that the company is exploring ways to deepen cooperation with Japanese memory chip customers and suppliers, and is cautiously assessing how to jointly develop the NAND flash memory market. Regarding the company's significant indirect stake in Kioxia, he mentioned that there are currently "no definite plans."After Toshiba's recent divestment, SK Hynix's investment vehicle BCPE Pangea Cayman2 has become Kioxia's largest shareholder, holding a 14.19% stake. SK Hynix holds bonds that can be converted into nearly all voting rights of this investment vehicle; according to a previous agreement, its voting rights cannot exceed 15% before 2028 without Kioxia's consent.In addition, SK Hynix is investing over $4 billion to build its first U.S. HBM packaging facility in Indiana. The cleanroom of the factory is expected to be operational by October 2028, with mass production of the next generation HBM planned for the second half of 2029, and it is expected to employ about 1,000 people once fully operational. The company is also still evaluating the possibility of listing its U.S. NAND subsidiary Solidigm, but no decision has been made yet.

P Equity Research and SemiAnalysis researcher Nick Doyle and others discussed high bandwidth flash (HBF) in X Space. Nick stated that it is still too early to determine how much the cost premium of HBF relative to HBM can shrink; existing data mostly comes from vendor claims, such as Sandisk stating that the cost per bit is about one-eighth that of HBM. Yields, testing, and other factors will improve with scale, but structural costs such as TSV, stacking, and pSLC mode will always exist, and durability is a key unknown; if wear exceeds expectations, costs will rise.The application scenarios for HBF are narrow, targeting only AI inference, especially low batch and long context MoE models, and it is not a substitute for HBM. The actual bandwidth target is about 1.6 TB/s, which is at the HBM3E level, suitable for sequential reads to load model weights, more aligned with the capacity needs of a small number of GPUs in local or private enterprises, rather than ultra-large-scale bandwidth scenarios. Heat dissipation reliability has not yet been resolved; flash memory will degrade faster at high temperatures next to GPUs, and mitigation measures such as UCIe separation and daily refresh have yet to be validated.In terms of manufacturing, Sandisk/Kioxia has experience with 3D NAND, and SK Hynix complements HBM-style stacking capabilities, but mass production is still to be confirmed. Overall, storage is shifting towards a specialized layered market, with NAND shortages expected to continue until 2028, and HBF may further impact supply and demand.

According to Nikkei Asia, SK Hynix CEO Kwak Noh-Jung stated that the global shortage of memory chips is expected to last until the end of 2030, with a low risk of oversupply. He pointed out that in the AI era, memory chips are no longer just "commodities," and there are currently no signs of oversupply or industry downturn; demand from AI customers remains strong.SK Hynix is a major supplier to NVIDIA. The report stated that the company remains open to further expanding its investments in the U.S. after launching its first HBM chip packaging plant in Indiana.