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TSMC announced the latest monthly data, with revenue in August reaching 514.8 billion New Taiwan Dollars, a year-on-year increase of 53.3%.From January to August 2026, TSMC's consolidated revenue was approximately 3 trillion 386.87 billion New Taiwan Dollars, an increase of 39.3% compared to about 2 trillion 432 billion New Taiwan Dollars in the same period of 2025. In absolute terms, revenue in the first eight months increased by over 95 billion New Taiwan Dollars compared to the same period last year.

The Central Science Management Bureau confirmed on the 9th that TSMC's Central Science Phase II 1.4 nanometer factory expansion is fully accelerating. The first P1 factory has completed its steel structure and is expected to begin trial production in April next year, with mass production anticipated in the second half of next year, ahead of the originally scheduled mass production in 2028. TSMC has applied to the Central Science Management Bureau to set up two temporary offices at the site, which are expected to be completed in April next year, with the first batch of over 5,400 operational and outsourced personnel moving in.The advanced process new factory for TSMC's Central Science Phase II park broke ground last October, planning to build four 1.4 nanometer factories, with nearly 2,000 workers working day and night. The P1 factory is currently undergoing floor and exterior wall construction, with the factory building expected to be completed early next year. The P2 factory has begun basic construction and is scheduled to be completed in October next year, with both factories expected to start mass production successively next year. The P3 factory has obtained a construction permit, while the P4 factory is in the process of applying for a construction permit, planning to be built with a six-month gap. P3 is expected to be completed in the second quarter of 2028, and P4 is scheduled for completion in the fourth quarter of the same year. After the P2 factory is completed in the second half of next year, an additional 1,000 operational personnel will be added, with the total number of employees expected to be between 9,000 and 10,000 when all four new factories in Phase II are completed and put into production.

The supply chain reports that the capacity for high-end testing interfaces for AI chips is tight. NVIDIA has significantly raised prices to secure the capacity of mainstream testing interface vendors' probe cards and test sockets, causing some R&D and engineering validation demands to be squeezed out.Including wafer foundry TSMC and chip manufacturers, multiple supplier validations have been initiated to cope with the supply pressure after capacity has been locked.

On September 8, TSMC announced that starting in 2030, it will adopt a new "high NA" extreme ultraviolet (EUV) lithography machine manufactured by ASML from the Netherlands for mass production. Both parties also stated that they will carry out industry-wide improvements on the high NA machines. ASML monopolizes the supply of EUV lithography machines used to form nanoscale ultra-fine circuits and will begin shipping high NA machines capable of drawing finer circuits starting in December 2023. Intel has already introduced high NA machines, while TSMC previously delayed mass production due to high costs and other reasons.TSMC and ASML will launch an industry-wide project to enlarge the photomask, which serves as the original circuit pattern, from the current 6-inch (approximately 15 centimeters) square to a 12-inch square, and develop high NA machines and related components corresponding to the large masks. A large mask pilot production line is planned to be established before 2031, and the high NA machines corresponding to the large masks are expected to reach a state suitable for advanced semiconductor production before 2033. Major semiconductor manufacturers and mask companies have expressed interest in participating.High NA machines can draw finer circuits, but the area that can be drawn in a single exposure is reduced to half that of traditional models, requiring multiple exposures for large chip circuits, which complicates the process and increases costs. Enlarging the photomask can expand the exposure area and reduce costs. TSMC Chairman and CEO C. C. Wei stated that the company will gather expertise from the entire industry to continuously promote technological innovation that makes advanced technology widely usable and convey its benefits.

Taiwan Semiconductor Manufacturing Company, Micron, and other companies are increasing capital expenditures to expand production, driving the combined orders of the top five semiconductor engineering firms—HanTang, Axiom, FanXuan, Yankee, and ShengHui—to exceed 880 billion yuan, a record high. Taiwan Semiconductor Manufacturing Company recently stated at a semiconductor exhibition that it is building up to 20 wafer fabs, with the overall capacity expansion scale increasing multiple times compared to the past, but it still cannot meet customer demand. The U.S. tariff policy has driven the demand for manufacturing plants in the United States. Axiom has the largest order amount of 440.73 billion yuan, and Chairman Yao ZuXiang pointed out that the cumulative amount of turnkey projects undertaken in Singapore over the past four years has reached 600 billion yuan, with expectations for new projects to follow. HanTang's order amount is approximately 193.937 billion yuan, setting a new record, benefiting from continued plant construction by major clients like Taiwan Semiconductor Manufacturing Company and Micron.FanXuan's order amount reached a new high of 135.1 billion yuan, and Chairman Gao XinMing revealed that order visibility extends at least to 2028, with related projects for clients planned for 2029 and 2030. FanXuan has deployed materials, manpower, and local construction teams to support clients in Taiwan, Arizona in the United States, Japan, and Germany in synchronizing production expansion needs, and is investing in the development of technologies such as CoPoS. ShengHui's order amount exceeds 60 billion yuan, with Taiwan accounting for 68% and semiconductor orders accounting for 63%. In the first half of the year, the after-tax net profit was 2.944 billion yuan, with earnings per share of 23.73 yuan, setting a new high for the same period. Yankee's after-tax net profit in the first half of the year was 2.317 billion yuan, with earnings per share of 17.46 yuan, and the order amount is approximately 51.77 billion yuan, with order visibility reaching the end of 2027.

According to a report by the Economic Daily, with the rising demand for AI and high-performance computing applications, TSMC is expanding its capacity for advanced processes below 3 nanometers at the request of its customers.Industry insiders are optimistic that TSMC's contribution from 3 nanometers in the second half of the year is expected to surpass that of 5 nanometers for the first time, estimating that the single-quarter output value in the third quarter will exceed 400 billion New Taiwan dollars, setting a new record, accounting for more than 30% of revenue, and positively impacting gross margin performance.

On September 2, TSMC Senior Vice President and Co-COO Dr. Wei-Chung Hou stated that the speed of change in AI demand far exceeds past industry experiences. Taking TSMC's equipment demand as an example, the estimated equipment needed for this year at the end of last year was calculated to be 1 times, but just one quarter later it increased to 1.5 times, and by July of this year, it had reached 1.9 times, with demand nearly doubling in just six months.Dr. Hou pointed out that the semiconductor industry has never faced such rapid changes in demand in the past 30 years. The entire industry needs to provide nearly double the original equipment, capacity, and resources in an extremely short time. TSMC is currently constructing 13 fabs in Taiwan and about 5 to 6 overseas, totaling nearly 20 fabs globally, with the scale of construction expanded to about 3 to 4 times that of the past, yet still unable to fully meet customer demand.He emphasized that in the AI era, the entire system or module needs to be optimized, and traditional collaborative models can no longer meet the demand. The supply chain must be restructured into a new cooperation model that is more closely integrated. The entire ecosystem is not yet prepared for such rapid growth, with equipment demand nearly doubling in six months, and almost no suppliers can completely avoid capacity constraints.

According to sources in the materials industry, on September 2, TSMC is expected to continue using traditional micro-bump technology rather than hybrid bonding in the short term for connecting high-bandwidth memory (HBM) with AI accelerators in advanced packaging. Considering the development cycle of related materials, finer pitch micro-bumps are expected to be used until the later stages of HBM4 and the early stages of HBM5. TSMC has requested its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micron bumps, with suppliers from South Korea and Japan beginning development, and mass production of 5μm bumps expected to start in the second half of 2028.Currently, the bump height of the third-generation extended HBM, namely HBM3E, is about 15-25μm, while HBM4 is close to about 10μm. Japanese material suppliers have previously stated that it is difficult to guarantee quality below 15μm. The reduction and refinement of bumps are due to the height limitations of HBM cubes and the demand for higher interconnection density. JEDEC specifies that the maximum height for HBM stacks is 775μm. In TSMC's advanced CoWoS packaging, the HBM stacks assembled by GPU and memory suppliers are mounted onto the silicon interposer via micro-bumps, with the 16-layer DRAM chip stacks completed within HBM packaging by SK hynix and Samsung Electronics.The first and second generations of HBM used larger solder bumps, while micro-bumps became mainstream around the HBM3 generation. SK hynix uses the MR-MUF process, while Samsung Electronics uses TC-NCF. Hybrid bonding allows for thinner and denser interconnections through direct bonding of copper pads; TSMC has utilized this on its SoIC platform for logic chip stacking, but HBM still connects to the interposer using micro-bumps.

According to a report by Juheng.com, after Samsung Electronics took the lead in raising prices for some advanced and mature processes, the market expects TSMC to follow suit, with prices for its various processes likely to increase by 10% to 15% across the board. According to reports from TrendForce and Nomura Securities, TSMC has completed a new round of price negotiations with customers in mid-year, raising prices for the tight supply of some 3-nanometer N3 processes by up to 15% for the second half of the year. The market further anticipates that by early 2027 at the latest, prices for TSMC's advanced processes such as N2, N3, and N5 may increase by another 5% to 10%.TSMC's N2 and N3 capacities have almost been fully booked by Apple and NVIDIA. The prices for mature processes such as N12, N16, and N28, which have not been adjusted for three consecutive years, may also see a simultaneous increase, with a maximum rise of about 10%. According to estimates from Citi Securities, TSMC's capital expenditure will reach $80 billion in 2027, further increasing to $90 billion in 2028, with this year's capital expenditure already raised to between $52 billion and $56 billion. TSMC announced in July that it would expand its investment in the United States to $265 billion. According to Reuters, Samsung raised prices for some new orders of advanced processes in July, with the 4-nanometer SF4 seeing increases of 10% to 15% for customers in China and the United States.

Apple's first 2-nanometer M6 chip officially debuts, equipped with a 12-core CPU, 12-core GPU, and dual 16-core neural network engines, with unified memory bandwidth reaching up to 170GB per second, initially featured in the new Mac mini. This chip is manufactured by TSMC using a 2-nanometer process and is the first to adopt gate-all-around (GAA) nanosheet transistors, making it the world's first consumer-grade 2-nanometer chip.The supply chain is focused on the subsequent high-end M series packaging architecture. Based on the Fusion Architecture of the previous generation M5 Pro, M5 Max, and the four-die design of M5 Ultra, Apple chips have transitioned from a single large die to a modular design. Future M6 Pro, Max, or Ultra are expected to enhance advanced packaging requirements such as SoIC-MH and WMCM, increasing interconnect density with SoIC-MH and integrating logic, LPDDR memory, and high-speed I/O with WMCM.TSMC is actively preparing for expansion, with Zhunan AP6 as the main mass production base for SoIC, Longtan AP3 upgrading to WMCM, and Chiayi AP7 taking on related capacity. Analysts estimate that WMCM's monthly production capacity will reach about 60,000 units by the end of 2026 and over 120,000 units in 2027. Equipment manufacturers such as Hongshuo, Junhua, Yinneng, and material manufacturers Changxing, Xinying Materials, and Yongguang are expected to benefit.

According to the Industrial and Commercial Times, there are widespread rumors in the market that TSMC intends to invest over 30 billion New Taiwan dollars to acquire AUO's two old-generation panel factories, L7 and L5C, located in the Central Taiwan Science Park, adjacent to TSMC's plant, to reserve space for large-size packaging such as CoPoS and FOPLP. Informed sources indicate that TSMC has sent personnel to complete on-site audits, and AUO plans to prioritize the disposal of the two factories, aiming to submit to the board of directors in October, with an estimated completion of production line relocation and factory vacating by the end of the first quarter next year. Both TSMC and AUO have not confirmed this transaction.Semiconductor industry analysts suggest that TSMC is extending from the A14 advanced process and advanced packaging to the COUPE silicon photonics platform, leveraging Taichung's role as a hub for precision optical components to build the Central Taiwan Science Park into a CPO ecosystem. TSMC's existing Fab 15A in the Science Park mainly uses a 28-nanometer process and can support the manufacturing of silicon interposers; the second phase of the Science Park, Fab 25, is planned to build four A14 wafer fabs, with the first two already entering steel structure construction, and the first factory striving for completion before April 2027. The existing advanced packaging and testing facility AP5 in the Science Park has already started CoWoS production, and in the future, it will integrate electronic and photonic chips through the COUPE platform.On the optical side, Largan Precision has recently acquired land and factories in Nantun, Taichung Industrial Zone, and nearby precision machinery clusters, with three transactions totaling approximately 2.568 billion, interpreted by the market as a warm-up for CPO mass production. The company has obtained its first mass production order for fiber optic arrays, with the first automated trial production line aiming for completion by the end of the third quarter, and mass production expected as early as mid-2027, while also laying out micro-lens arrays and integrated FAUs.

According to reports from Liberty Times and other media, TSMC has completed the development and verification of the angstrom-level A16 (1.6nm) process, which is expected to enter mass production in the fourth quarter of 2026. This process uses TSMC's back-end power delivery network technology Super Power Rail (SPR), separating signal routing from power routing, with the power located on the back of the wafer to reduce bottlenecks.Compared to the 2nm process, the A16 is said to improve computing speed by 8% to 10%, reduce energy consumption by 15% to 20%, and increase chip density by 8% to 10%. TSMC views the 1.6nm process as a transitional step towards 1.4nm, with the goal of starting 1.4nm mass production in 2028.

According to the Industrial and Commercial Times, competition in advanced process technology for PC processors is heating up. Market news indicates that Intel's next-generation Nova Lake desktop processor will prioritize the introduction of bLLC large last-level cache to reduce access latency to system memory, competing with AMD's 3D V-Cache technology; the laptop version may be delayed until the subsequent Razor Lake-HX generation is released. The supply chain reveals that Nova Lake, set to debut early next year, will utilize a combination of Intel's 18A and TSMC's N2P processes, while the subsequent Razor Lake may further adopt TSMC's high-performance 2-nanometer N2X process.N2X is a high-performance extension of TSMC's N2 platform, targeting high-frequency CPUs, AI, and HPC applications, with transistor technology shifting from FinFET to nanosheets. If mass production is achieved, Intel's collaboration with TSMC on advanced processes is expected to extend to a broader 2-nanometer family, helping to reduce risks associated with a single proprietary process and optimize the timing and capacity configuration for high-end CPU launches.In addition to TSMC benefiting directly, related supply chains are also expected to welcome business opportunities. Sungsan is one of the few manufacturers in Taiwan capable of mass-producing its own CMP polishing pads, with a 25% year-on-year increase in consolidated semiconductor revenue in the first half of the year, rising to 66% of total revenue. Demand for Hard Pads and advanced packaging is strong, with a new Soft Pad line expected to begin trial production in the third quarter and gradually ramp up production in the fourth quarter, with products already applied in CoWoS and SoIC. Zhongsha holds CMP diamond discs and recycled wafers, reporting revenue of 2.49 billion yuan in the second quarter, a year-on-year increase of 17.9%, with gross margin rising to 40.1%, and shipments of 2-nanometer and 1.6-nanometer related diamond discs rapidly increasing.

According to the Economic Daily, TSMC's advanced packaging CoWoS capacity is in short supply, and it has been reported that some backend orders have overflowed to Intel's factory in Malaysia, where Intel is assisting with packaging using part of its capacity to serve common major customers, breaking the past ecosystem competition norms. TSMC Chairman Wei Zhejia previously stated at a conference call that TSMC focuses on advanced packaging in the frontend and welcomes "more manufacturers to supply capacity" for the shortage in the backend, providing flexible alternatives for common customers.The report points out that the bottleneck in advanced packaging capacity mainly lies in the backend ramp-up speed being lower than that of the frontend process, and the widening gap in CoWoS capacity has forced orders to overflow. SemiAnalysis Chipbook data shows that approximately $1.3 billion worth of HBM has been shipped to Malaysia, and industry analysis indicates that Intel's local factory should already have the capability for large-scale HBM integration. Intel CEO Pat Gelsinger stated that the EMIB-T technology is ensuring reliable yield, and in the context of insufficient CoWoS capacity, "Intel is in a unique position to provide support." Companies with overlapping supply chains such as Unimicron, ASE Technology Holding, and Jiadeng are expected to benefit simultaneously, with Unimicron's stock price rising over 7% on that day. Intel's EMIB-T related applications are targeted for mass production by 2027.

Tiger Global Fund made significant adjustments in the second quarter, reducing its holdings in Broadcom by 51.1% to 1.8 million shares, Google A by 45.4% to 5.8 million Class A shares, TSMC by 12.3% to 4.9 million ADS, Microsoft by 9.3% to 2.3 million shares, Meta Platforms by 8.5% to 2.8 million Class A shares, NVIDIA by 6.8% to 11.2 million shares, and JD.com by 41.5% to 201,500 ADS.Increased holdings in Intel to 4.3 million shares, established new positions in AMD with 674,000 shares and SpaceX with 375,000 shares, and completely exited Netflix.

The U.S. Securities and Exchange Commission (SEC) documents show that SoftBank Group has reduced its stake in TSMC by 71.5%, down to 565,000 American Depositary Receipts.

According to DIGITIMES, NVIDIA's next-generation AI platform Feynman aims for mass production in the second half of 2028, utilizing TSMC's A16 process and incorporating SoIC 3D stacking and CPO technology. The Rubin generation focuses on integrating multiple small chips with HBM, while Feynman further develops towards 3D small chips, SoIC, and CPO. The report indicates that TSMC is accelerating the construction of related production capacity, with the original plan for SoIC monthly capacity to reach 20,000 pieces by the end of 2026, now updated to a target of 50,000 pieces by the end of 2027.The construction progress of TSMC's Chiayi AP7 and Tainan AP8 is also accelerating, with AP7 planned in 8 phases. P1 and P2 have entered installation, P3 and P4 have obtained construction permits, and P5 to P8 are still in planning. In addition to mass-producing Apple-specific WMCM, the factory will configure SoIC, CoPoS, and CPO production lines according to customer demand. NVIDIA has rapidly shifted its R&D and supply chain resources to the Feynman platform, and the spillover effect of TSMC's advanced packaging orders continues to expand, with Siliconware becoming the main testing and packaging factory for NVIDIA's CoWoS and CPO orders. The NVLink interconnect bandwidth of NVIDIA's Feynman platform is expected to exceed 1 PB/s, further improving from Rubin Ultra's 520 TB/s. TSMC's COUPE technology integrates EIC and PIC in 3D through SoIC to form a light engine, advancing optoelectronic conversion from traditional circuit boards to the internal packaging structure. Since 2026, NVIDIA has invested over $40 billion in building the AI ecosystem, covering areas such as models, wafer manufacturing, data centers, and optical communications.

On August 11, TSMC held a board meeting and approved a capital budget of approximately $29.443 billion to expand advanced process and advanced packaging capacity to meet the strong demand brought by AI and high-performance computing. In May of this year, the board had already approved $31.283 billion, bringing the total approved capital budget for the year to $60.726 billion (approximately NT$1.96 trillion). TSMC Chairman C.C. Wei stated at the July earnings call that in the coming years, 13 advanced wafer fabs and advanced packaging plants will continue to be built in Taiwan, covering Kaohsiung, Hsinchu Baoshan, and Tainan, with the total investment scale in Arizona, USA also increasing to $26.5 billion.The board also approved the establishment of a joint venture with Sony Semiconductor Solutions Corporation, with TSMC's investment cap set at 282 billion yen. The joint venture will be located in Kumamoto Prefecture, Japan, aiming to mass-produce next-generation image sensors for smartphones by 2029. In addition, the board approved a cash dividend of NT$7 per share for the second quarter, with the ex-dividend date set for December 10. TSMC will provide eligible foreign shareholders with the option to receive cash dividends in US dollars.

Microsoft plans to publicly release its next-generation Maia 300 AI chip this fall (possibly as early as September). To meet delivery demands for 2027, Microsoft has engaged with TSMC to secure manufacturing capacity for over 300,000 units of the chip.

TSMC announced its revenue report for July 2026, with consolidated revenue of approximately NT$467.58 billion (about US$14.3 billion), a quarter-on-quarter increase of 5.6% and a year-on-year increase of 44.7%. The cumulative revenue from January to July 2026 was approximately NT$2.872 trillion (about US$87.9 billion), a year-on-year increase of 37.0%.In its second-quarter financial report, TSMC stated that demand related to AI remains strong, with HPC and advanced process orders being the main growth drivers. It is expected that annual revenue in US dollars can achieve a mid-to-high double-digit growth. The company is actively promoting the expansion plans for advanced processes such as 2nm and 1.4nm, while the capacity for advanced packaging like CoWoS is also continuously expanding.