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Flash

first_img Samsung's 4-nanometer production capacity is more than half used for HBM4 substrate chips

Samsung Electronics' wafer foundry division has recently surpassed 50% in the allocation of production capacity for the sixth-generation high bandwidth memory HBM4 substrate chips in the 4-nanometer process. The industry states that this division will invest more than half of its 4-nanometer wafers into HBM4 substrate chip manufacturing in the second half of this year to expand supply to companies like NVIDIA, Broadcom, and AMD.Samsung initiated mass production and shipment of HBM4 in February this year and plans to increase supply starting from the third quarter, significantly increasing the related wafer input since mid-year. This chip is based on Samsung's wafer foundry 4-nanometer (SF4) process. As of last month, over 50% of its total 4-nanometer capacity has been allocated to HBM4 substrate chips. According to insiders, Samsung's 4-nanometer process is currently at full capacity, with HBM4 substrate chips accounting for about 50% to 60%, and this high proportion will be maintained in the second half of the year.Samsung's wafer foundry production lines at Pyeongtaek Plant 2 and Plant 3 are mass-producing processes ranging from 4 to 7 nanometers, with a monthly capacity of about 30,000 wafers for the 4-nanometer process. Based on this, the wafer input related to HBM4 substrate chips is estimated to be about 15,000 wafers per month. During the second quarter earnings call, Samsung stated that it expects HBM4 revenue to increase more than threefold quarter-over-quarter in the third quarter, with HBM4 revenue in the second half expected to exceed 60% of the company's overall HBM revenue.

first_img Micron plans to expand HBM production capacity to approximately 100,000 wafers per month by the end of the year

According to Electronic News on September 3, Micron plans to double its high bandwidth memory (HBM) production capacity compared to last year, with a maximum addition of 60,000 wafers per month by the end of this year. Insiders say that Micron's HBM output was about 40,000 to 50,000 wafers per month last year, and it is expected to reach about 100,000 wafers per month by the end of the year, narrowing the gap with Samsung Electronics and SK Hynix.Micron is increasing procurement orders from multiple HBM equipment suppliers, with production bases mainly in Taiwan and Singapore, continuously introducing equipment. Currently, the output is mainly HBM3E 12-layer, with HBM4 12-layer accounting for about 20% to 30% at the beginning of this year, which may rise to as high as 50% by the end of the year. HBM4 12-layer will be used in NVIDIA's latest AI accelerator, Vera Rubin, and Micron has started mass production of this product since the second quarter of this year.Micron CEO Mehrotra stated in the Q3 earnings call for fiscal year 2026 in June this year that the ramp-up speed of HBM4 12-layer mass production is about twice that of HBM3E 12-layer, and cumulative revenue from HBM4 shipments has exceeded $1 billion. The industry believes that Samsung and SK Hynix each have HBM production capacities of about 150,000 to 200,000 wafers per month. Counterpoint data shows that in Q2 of this year, the global HBM market shares were SK Hynix 50%, Samsung 32%, and Micron 18%. Micron is also preparing related investments in Hiroshima, Japan.

first_img TSMC temporarily uses micro-bump packaging for HBM and requires the development of a 5μm solution

According to sources in the materials industry, on September 2, TSMC is expected to continue using traditional micro-bump technology rather than hybrid bonding in the short term for connecting high-bandwidth memory (HBM) with AI accelerators in advanced packaging. Considering the development cycle of related materials, finer pitch micro-bumps are expected to be used until the later stages of HBM4 and the early stages of HBM5. TSMC has requested its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micron bumps, with suppliers from South Korea and Japan beginning development, and mass production of 5μm bumps expected to start in the second half of 2028.Currently, the bump height of the third-generation extended HBM, namely HBM3E, is about 15-25μm, while HBM4 is close to about 10μm. Japanese material suppliers have previously stated that it is difficult to guarantee quality below 15μm. The reduction and refinement of bumps are due to the height limitations of HBM cubes and the demand for higher interconnection density. JEDEC specifies that the maximum height for HBM stacks is 775μm. In TSMC's advanced CoWoS packaging, the HBM stacks assembled by GPU and memory suppliers are mounted onto the silicon interposer via micro-bumps, with the 16-layer DRAM chip stacks completed within HBM packaging by SK hynix and Samsung Electronics.The first and second generations of HBM used larger solder bumps, while micro-bumps became mainstream around the HBM3 generation. SK hynix uses the MR-MUF process, while Samsung Electronics uses TC-NCF. Hybrid bonding allows for thinner and denser interconnections through direct bonding of copper pads; TSMC has utilized this on its SoIC platform for logic chip stacking, but HBM still connects to the interposer using micro-bumps.

SK Hynix considers Intel as the next-generation HBM substrate chip supplier

According to Citrini analyst Jukan, SK Hynix is working on diversifying the foundry suppliers for the substrate chips used in high bandwidth memory (HBM), which are constructed by vertically stacking multiple memory chips. It is reported that the company is considering outsourcing part of the substrate chip production for the seventh generation HBM, namely HBM4E, to Intel's foundry. So far, SK Hynix has relied entirely on TSMC for outsourcing substrate chip production.This move is seen as an effort to establish a multi-supplier foundry strategy to reduce the concentration of the supply chain on TSMC while enhancing SK Hynix's bargaining power in pricing. According to industry insiders on August 31, SK Hynix is advancing a plan where the substrate chips for HBM4E may be jointly manufactured by TSMC and Intel, potentially starting from the HBM4E generation.As the market expects the cost burden of substrate chips for HBM4E to further increase. Since HBM products are mainly covered by long-term supply agreements (LTA), SK Hynix also finds it difficult to immediately pass on the higher foundry costs to customers by raising product prices. Therefore, industry observers believe that if Intel ultimately joins SK Hynix's substrate chip supply chain, the company will gain more options in terms of cost competitiveness and supply stability.

first_img Samsung develops NVIDIA's custom NVHBM to advance 8-layer high-speed HBM4E

According to reports from Seoul Economic Daily, Samsung Electronics is developing HBM4E (seventh generation) 8-layer products that meet NVIDIA's requirements, aiming to secure its position as a core partner in the supply of customized high-bandwidth memory NVHBM. This product reduces the stacking height compared to the originally planned 12-layer and 16-layer designs. The speed specifications proposed by NVIDIA are 17-18Gbps, which is about 20% higher than the speed of Samsung's initial HBM4E samples (14.4Gbps), and will be used for NVIDIA's publicly disclosed NVLink optimized specifications for NVHBM.The use of 8 layers, contrary to the previous logic of increasing capacity by adding more stacking layers in HBM, can reduce the difficulty of post-processing and yield pressure, which is beneficial for expanding supply and is seen as NVIDIA's strategy to alleviate memory shortages. NVHBM is expected to be applied starting with the next-generation AI GPU "Rubin Ultra," which is set to launch next year. This GPU will expand the interconnection scale between GPUs from a maximum of 72 to 576, enhancing overall computing power through hundreds of GPUs equipped with faster HBM.In the customized HBM market, Samsung is more competitive compared to SK Hynix and Micron, as NVHBM requires DRAM and the production capabilities of logic chip-based bare die designs, which Samsung can integrate. Industry insiders say that Samsung has verified the highest speed levels in HBM4, which can provide an advantage in speed competition.

first_img SemiAnalysis: HBF non-HBM alternative, cost and heat dissipation still have uncertainties

P Equity Research and SemiAnalysis researcher Nick Doyle and others discussed high bandwidth flash (HBF) in X Space. Nick stated that it is still too early to determine how much the cost premium of HBF relative to HBM can shrink; existing data mostly comes from vendor claims, such as Sandisk stating that the cost per bit is about one-eighth that of HBM. Yields, testing, and other factors will improve with scale, but structural costs such as TSV, stacking, and pSLC mode will always exist, and durability is a key unknown; if wear exceeds expectations, costs will rise.The application scenarios for HBF are narrow, targeting only AI inference, especially low batch and long context MoE models, and it is not a substitute for HBM. The actual bandwidth target is about 1.6 TB/s, which is at the HBM3E level, suitable for sequential reads to load model weights, more aligned with the capacity needs of a small number of GPUs in local or private enterprises, rather than ultra-large-scale bandwidth scenarios. Heat dissipation reliability has not yet been resolved; flash memory will degrade faster at high temperatures next to GPUs, and mitigation measures such as UCIe separation and daily refresh have yet to be validated.In terms of manufacturing, Sandisk/Kioxia has experience with 3D NAND, and SK Hynix complements HBM-style stacking capabilities, but mass production is still to be confirmed. Overall, storage is shifting towards a specialized layered market, with NAND shortages expected to continue until 2028, and HBF may further impact supply and demand.
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