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Aave executed an adjustment to the USDT lending rate parameters in the Ethereum Core market at block height 26,241,799, lowering the rate inflection point from 94% utilization to 92%, causing borrowing costs to rise earlier when liquidity in the pool tightens. The new parameters are: optimal utilization rate 92%, base rate 0, first slope 4.5%, second slope 10%; the inflection point rate is 4.5% APR, reaching 14.5% APR when utilization hits 100%.At 94% utilization, the old curve's lending rate was 4.5% APR, while the new curve is 7% APR, an increase of 2.5 percentage points. LlamaRisk recommended the adjustment on October 20; based on a supply of 2.8922 billion USDT, a 92% utilization rate leaves approximately 57.84 million USDT unborrowed as a buffer compared to 94%. This buffer does not represent actual cash, and withdrawals still depend on available unborrowed liquidity. Snapshots show that the actual cash in the pool is about 391.4 million USDT, with a variable lending APR of about 4.23% and a supply liquidity APR of 3.29%.

According to Beating AI's news, a summary of an expert interview circulating in the investment community states that the next-generation foundational model of the artificial intelligence company Zhipu is not the previously rumored 1.6 trillion parameters, but rather between 2.5 trillion and 3.5 trillion parameters. The GLM-5.3 released by Zhipu in August this year still uses the previous generation foundational model, with a total of approximately 744 billion parameters; if the information is true, the new foundational model's scale is about 3.4 to 4.7 times that of the current one.The summary also states that the training has not gone smoothly, as Zhipu adopted a more aggressive model architecture, and during the pre-training period, there was a time when the loss did not decrease, meaning that computational power was continuously invested but training metrics could not continue to improve. The interviewee believes that the problem should have been resolved recently, and training is expected to be completed soon, predicting that the new model can reach flagship levels comparable to Claude Fable.The summary further mentions that the new model has taken inference speed and cost as hard constraints from the architectural design stage, with the goal of being able to provide services on a large scale from the first day of release. At the same time, multiple cloud vendors are negotiating revenue sharing to address the issue of large models being produced but not being able to supply.

According to the New York Post, Brad Gerstner, founder and CEO of investment firm Altimeter Capital and promoter of the Trump account plan, stated that he is pushing to expand the scope of the plan from those under 18 to those under 40. Related legislation may advance in the coming months and seeks to make the funding support mechanism permanent.Gerstner expects that by the end of 2027, private donations received by the plan could total $100 billion, and Musk's commitment to donate SpaceX stock to American children is just "the tip of the iceberg." Bloomberg ETF analyst Eric Balchunas estimated while relaying the report that the expansion could additionally cover about 100 million people. Currently, the expansion remains a legislative proposal in progress and is not an enacted policy.

According to a report by North Korea Biz on October 20, Samsung Electronics' foundry division has seen its 4-nanometer process capacity nearing full load due to an increase in customer orders, while the company is also expanding efforts to attract new customers for its 5-nanometer process. The report states that contracts for the most advanced 2-nanometer process with major global tech companies are still delayed, prompting Samsung to increase the utilization rates of its relatively stable 4-nanometer and 5-nanometer processes to improve profitability.The 4-nanometer process is used for smartphone application processors, artificial intelligence semiconductors, and high-performance computing chips. The report indicates that not all chips in the expanding artificial intelligence semiconductor market require the most advanced processes; the manufacturing costs of 4-nanometer and 5-nanometer processes are relatively low while still achieving high performance, making them suitable for certain artificial intelligence inference chips and application-specific integrated circuits.Regarding the 2-nanometer process, Samsung is in discussions with major global tech companies about production contracts, but some negotiations are taking longer than originally expected. In addition to yield rates, the most advanced processes also require comprehensive verification of energy efficiency, design assets, and stable mass production capabilities, which means a longer time frame from contract signing to mass production. Samsung views the 2-nanometer process as the core growth driver for its next-generation foundry business and plans to continue using the fully surrounded gate transistor structure first introduced in the 3-nanometer process to improve energy efficiency and performance.

According to the Industrial and Commercial Times, Japan's Ministry of Economy, Trade and Industry has approved TSMC's first phase plan for the production of advanced semiconductors using 3-nanometer process at its second factory in Kumamoto Prefecture. This will be the first time a manufacturer in Japan produces 3-nanometer chips. TSMC can further expand its production capacity based on additional support from the Japanese government. Kumamoto Prefectural Governor Seiji Kimura stated that this plan will drive a new wave of creative revitalization.The Nikkei reported that the Ministry of Economy has listed the Kumamoto second factory as a recipient of subsidies, with plans to produce 3-nanometer chips, expected to officially start production in December 2028, with final capacity depending on the amount of subsidies. The Ministry will include the budget needed for subsidies in the fiscal year 2027 budget request, with the Japanese government originally planning to provide 732 billion yen in subsidies. The Asahi Shimbun pointed out that the Kumamoto second factory is still under construction and is adjacent to the already operational Kumamoto first factory.Previously, TSMC planned for the second factory to manufacture 6-nanometer and 12-nanometer processes, with a monthly capacity of 48,000 wafers, and planned to produce 40-nanometer chips; in February this year, the plan was changed to 3-nanometer, reducing the monthly capacity to 6,000 wafers. The adjustment plan for the Kumamoto first factory was also approved by the Ministry, with the original plan to produce 55,000 wafers per month covering 22 to 28 nanometers and 12 to 16 nanometers, while the new plan stops production of 12 to 16 nanometers, changing to 45,000 wafers per month for 22 to 28 nanometers.

According to a report by Central News Agency citing Reuters, Microsoft announced the launch of its third-generation self-developed AI chip, Maia 300, with plans to deploy over 1 million units next year to support internal AI services. The small chip responsible for key computing functions uses TSMC's 2-nanometer process. The Maia 300 can handle code writing and perform complex business tasks on behalf of users. The previous generation of chips has been used to run Microsoft's internal AI models and the OpenAI models provided through Microsoft Azure cloud computing services.Microsoft is taking a different technological approach compared to NVIDIA. The NVIDIA AI accelerator uses a large computing chip surrounded by high-bandwidth memory chips; the Maia 300 core processing unit is composed of small chips, with the small chips responsible for key computing functions using TSMC's 2-nanometer process, while other small chips use the lower-cost 3-nanometer process to handle data transmission out of the processor and transfer data to other locations within the system.The Maia 300 will be installed in cabinets, with each cabinet accommodating 96 chips and consuming about 167 kW of power. In contrast, NVIDIA's latest GB300 AI server cabinet is configured with 72 GPUs and consumes about 142 kW of power. Microsoft stated that it plans to deploy the Maia 300 on a large scale starting next year, reaching several gigawatts. Microsoft previously indicated that it expects its capital expenditures to exceed $175 billion this year.

Papertrade's official response to the allegations of price manipulation and the existence of obvious loopholes in the protocol states: It has never been possible for small orders to have the same priority as large orders. If this were done, the front end would suffer from congestion due to junk trading, and the consequences would be much worse than the existing queuing mechanism.Under these constraints, we have designed the fair launch to be as inclusive as possible.Last night, the attempts to manipulate BTC/ETH on Hyperliquid BBO were not due to flaws in the mechanism that took six months to design. These situations had already been considered; it was only because the position limits were set very loosely in the early stages to cope with congestion that such occurrences were possible. If position limits were set during peak demand for launching, it would only exacerbate the slow experience, and the queuing mechanism itself, due to the uncertainty of opening/closing confirmation times, naturally provides protection against manipulation.As congestion eases, we have begun to tighten position limits on-chain and at the relay level. In such a system, manipulation attacks are always possible— the key is whether the attempt is economically viable. The official goal is to set parameters to a point where it is almost never profitable; even if successful, the tail risk is extremely high, and the expected value is negative.

According to a report by Nomura Securities, the AI company Dark Moon is developing a large model with 50 trillion to 60 trillion parameters. Compared to the Kimi K3 released in July this year, the parameter scale of the new model is nearly doubled. The report states that the current biggest bottleneck is the lack of high-end training computing power, and the specific training progress is still unclear.Additionally, according to the aforementioned news, Kimi K3.1 will be released before mid-October, focusing on enhancing the Agent's ability to continuously complete long-duration tasks. The team plans to further optimize the model through post-training, computer operation records, and real task data. The related content is a paraphrase and not an official announcement from Dark Moon.

According to the Economic Daily, major companies such as Apple, NVIDIA, AMD, Qualcomm, and MediaTek are racing towards AI and high-performance computing, recently increasing their orders for TSMC's 2-nanometer family capacity by 10% to 20%. As a result, TSMC is accelerating the expansion of its 2-nanometer family, with progress exceeding expectations. TSMC has consistently refrained from commenting on customer information and market rumors.The market originally estimated that TSMC's monthly capacity for the 2-nanometer family would be around 90,000 to 100,000 wafers by the end of this year, with expectations for continued double-digit growth to reach 110,000 to 140,000 wafers by 2027. Industry sources indicate that due to strong customer demand, the monthly capacity is expected to surge to 120,000 wafers by the end of this year, achieving the originally set 2027 target ahead of schedule. Sources say that in response to the demands from Apple and non-Apple customers, the speed and scale of new capacity for the 2-nanometer family are setting new records, far exceeding the ramp-up speed of the 3-nanometer family in its first year.TSMC's Senior Vice President and Co-COO, Wei Chen-Hao, stated at this year's North America Technology Forum that in response to strong demand from AI and other sectors, there will be five 2-nanometer fabs ramping up simultaneously for the first time this year, including two in Hsinchu and three in Kaohsiung; the wafer output in the first year of 2-nanometer will increase by 45% compared to the first year of 3-nanometer in 2023; the compound annual growth rate of 2-nanometer capacity from 2026 to 2028 will reach 70%. TSMC's 3-nanometer capacity in the Southern Taiwan Science Park is expected to reach nearly 180,000 wafers per month in the fourth quarter of this year, and three new 3-nanometer fabs are being established in Taiwan, Arizona in the United States, and Japan. The second fab in the United States is planned to begin mass production in the second half of 2027.

According to Blockaid monitoring, Meter.io's Meter Passport on the BNB Chain is under attack. The attackers are minting a large amount of uncollateralized wrapped tokens wMTRG through cross-chain channels and have already sold some of the tokens on PancakeSwap.Currently, the attackers have minted approximately $2.3 million worth of wMTRG through about two transactions, and the attack is still ongoing.

Semiconductor analysis firm Kernel Insight: Demand for artificial intelligence drives DRAM prices to maintain historical highs, with the unit area sales value of the latest process DRAM exceeding the wafer prices of TSMC's N2 and N3. The firm estimates TSMC's 300mm N3 wafer price at $20,000 and N2 at $30,000, translating to nominal prices of approximately $0.283 per square millimeter and $0.424 per square millimeter, respectively, not accounting for edge losses, cutting losses, yield, and defects.Based on a price of $1.50 per Gb and generational bit density calculations, 1y DRAM is $0.329 per square millimeter, 1z is $0.410 per square millimeter, and 1b is $0.654 per square millimeter, more than 50% higher than N2. The 10nm process gradually shrinks in the order of 1y, 1z, 1a, and 1b. The above prices per Gb assume they are close to spot prices; DRAMeXchange data shows that on September 21, the average transaction price for 16Gb DDR5 eTT chips was $24.80, approximately $1.55 per Gb.There are differences in comparison metrics. TSMC's figures represent the wafer foundry prices paid by customers, while the DRAM figures represent the total sales potential of finished products and do not include advanced packaging costs; TSMC's actual supply prices will vary with order volumes and contracts. DRAM metrics are based on small spot prices, differing from the long-term contract prices of Samsung Electronics, SK Hynix, and Micron's revenue entities. Recently, non-public fixed trading prices have strengthened; if they have not yet fully reflected in spot prices, the leading margin of wafer unit prices for memory manufacturers may be even greater.

According to Money Today on September 21, Samsung Electronics is advancing the expansion of advanced process capacity in wafer foundry due to the growth of the HBM market. To meet the rising demand for HBM4 base chips, it is evaluating the expansion of its 4-nanometer process. Samsung's HBM4 consists of 10-nanometer 6th generation (1c) DRAM core chips and 4-nanometer logic base chips, with the base chips responsible for high-speed data exchange with AI accelerators such as GPUs.Unlike SK Hynix, which uses TSMC's 12-nanometer process for HBM4 base chips, Samsung employs its own 4-nanometer process. This production line is operating at full capacity and has taken on orders from companies like Nvidia and Groq for 3 LPU, and the company has recently raised its prices for new 4-nanometer orders and HBM4 base chips. Samsung expects HBM4 revenue in the third quarter to increase more than threefold quarter-on-quarter, with HBM4 accounting for significantly more than 60% of HBM revenue in the second half of the year. The additional expansion at P4 in Pyeongtaek will mostly be used for 1c DRAM for HBM, with more than half of the wafer foundry's 4-nanometer capacity allocated to HBM4 base chips.HBM4E also uses 4-nanometer base chips, and Samsung provided samples to customers in May. The company is also evaluating the construction of a new 2-nanometer production line for HBM5, aiming for a GAA structure 2-nanometer process and increasing TSV density to improve operating speed by more than 50% compared to HBM4E. Samsung started the first generation of 2-nanometer mass production in the second half of last year and is advancing the second generation of products in the second half of this year. Citigroup expects global HBM bit demand to reach 75.2 billion Gb next year, a year-on-year increase of 62%, with supply around 59.4 billion Gb and a gap of about 21%.

Market news reports that Alibaba plans to train an artificial intelligence model with parameters ranging from 50 trillion to 100 trillion.

DeepSeek CEO Liang Wenfeng revealed to investors that the company is training a 20 trillion parameter model and plans to develop an 80 trillion parameter model afterward. The current flagship V4-Pro has a total of 1.6 trillion parameters.Among the publicly disclosed ultra-large models, Moonshot AI's Kimi K3 reaches 2.8 trillion parameters. Kimi K3 uses the MoE architecture, with each token activating 104 billion parameters out of the total 2.8 trillion. The planned 80 trillion parameter model by DeepSeek is nearly three times that size.DeepSeek completed over 50 billion yuan in financing in July, with a valuation exceeding 50 billion dollars. V4-Pro is open-sourced with a total of 1.6 trillion parameters and 49 billion active parameters.

U.S. Vice President JD Vance stated at the All-In Summit that U.S. AI data centers are facing increasing opposition, largely because the power supply has not kept up. Residents see data centers being built continuously while their electricity bills are rising, which naturally leads to backlash. He believes the solution is not to build fewer data centers but to increase power generation capacity accordingly.Vance mentioned that the U.S. has not built enough power facilities in the past generation, and in the future, it should pursue a state where "electricity is so cheap that it doesn't need to be metered." He also compared this to China, arguing that the slow growth of power generation in the U.S. in recent years has already affected the development of new industries like AI. "So cheap that it doesn't need to be metered" is an old slogan from the history of U.S. nuclear energy. In 1954, Lewis Strauss, the chairman of the U.S. Atomic Energy Commission, used it to describe the era of cheap electricity brought by atomic energy.The IEA estimates that data centers will contribute to about half of the new electricity demand in the U.S. by 2025; the U.S. Congress is also advancing legislation this week to try to prevent the costs of expanding data centers from being passed on to ordinary households.

As we enter the late third quarter of 2026, TSMC's 3nm and 2nm advanced process and CoWoS advanced packaging capacity continue to be in high demand. NVIDIA and Apple continue to dominate the resources for advanced processes and packaging; Amazon AWS's Annapurna has recently increased its AI self-developed chip production, securing more 3nm capacity. MediaTek, in addition to mobile chips, is also competing for 2/3nm process and CoWoS-S/L capacity with large orders related to Google TPU.There are reports that TSMC has recently readjusted its capacity allocation. After MediaTek secured a large order from Google TPU, the next-generation TPU v9 will simultaneously use TSMC's CoWoS-L and Intel's EMIB-T, which has slightly adjusted MediaTek's 3nm and 2nm capacity arrangements. Currently, TSMC's main customer for 3nm is NVIDIA, which is expected to surpass Apple to become the largest customer by 2025; the demand for 2nm is primarily from Apple and others. After AWS increased Annapurna's production, its 3nm and CoWoS configuration priority has improved.Starting in early 2026, TSMC will accelerate capacity expansion, with the 2nm monthly capacity of Hsinchu Baoshan Fab 20 and Kaohsiung Fab 22 reaching 50,000 wafers each by the end of October, totaling about 100,000 wafers; by the end of October, the monthly capacity for 3nm in Tainan Science Park is about 185,000 wafers. As of the end of September, the overall capacity utilization rate is about 96.2%, with 100% utilization for processes below 16/12nm down to 2nm. The shortage of CoWoS supply has driven advanced packaging orders to overflow, with the priority for orders going to ASE Group's Siliconware Precision Industries first, followed by Amkor, and Chipbond, among others. Chipbond's related testing and packaging capacity is fully loaded, with order visibility extending to 2028.

The supply chain reveals that TSMC has disclosed its expansion targets for 2/3 nanometers for the first time next year. The 2-nanometer production is expected to increase from 90,000 wafers at the end of this year to 110,000 wafers by mid-next year, an increase of 22%; the 3-nanometer production is expected to rise from over 180,000 wafers at the end of this year to 210,000 wafers by mid-next year, an increase of over 16%. TSMC did not comment on market rumors yesterday and emphasized that capacity-related statements are based on the company's announcements.It is reported that TSMC's monthly capacity for 3 nanometers reached 120,000 to 130,000 wafers at the end of last year and is expected to expand to 180,000 wafers by the end of this year, with a target of over 210,000 wafers by mid-next year. The monthly capacity for 2 nanometers is expected to reach 90,000 wafers by the end of this year. TSMC previously stated that capital expenditures in 2026 will range from $60 billion to $64 billion, with approximately 70% to 80% allocated for advanced processes, and plans to add three 3-nanometer fabs located in Taiwan, Arizona in the United States, and Japan, while converting 5-nanometer equipment in Taiwan to support 3-nanometer capacity.

According to The Bell, Samsung Electronics' foundry division has delayed its contract for application processor foundry production with Qualcomm due to differences in production unit prices, and both parties have failed to narrow the price gap, prolonging negotiations. There have been no significant technical issues, and the currently discussed 2-nanometer process has received a considerable degree of stabilization evaluation.Industry sources indicate that the Qualcomm AP foundry using Samsung's 2-nanometer process may be postponed until next year, and it is unclear whether production can commence within this year. Qualcomm had previously entrusted advanced AP production to Samsung before 2021, and Samsung has been continuously striving to regain this business in recent years, having secured clients such as Tesla and Broadcom.Informed sources state that the contract delay has made it difficult for Samsung to produce APs for Qualcomm this year, and both parties may turn to discuss the next generation of products. After acquiring strategic clients, Samsung is no longer willing to accept low-price orders as it did in the past.

The Central Science Management Bureau confirmed on the 9th that TSMC's Central Science Phase II 1.4 nanometer factory expansion is fully accelerating. The first P1 factory has completed its steel structure and is expected to begin trial production in April next year, with mass production anticipated in the second half of next year, ahead of the originally scheduled mass production in 2028. TSMC has applied to the Central Science Management Bureau to set up two temporary offices at the site, which are expected to be completed in April next year, with the first batch of over 5,400 operational and outsourced personnel moving in.The advanced process new factory for TSMC's Central Science Phase II park broke ground last October, planning to build four 1.4 nanometer factories, with nearly 2,000 workers working day and night. The P1 factory is currently undergoing floor and exterior wall construction, with the factory building expected to be completed early next year. The P2 factory has begun basic construction and is scheduled to be completed in October next year, with both factories expected to start mass production successively next year. The P3 factory has obtained a construction permit, while the P4 factory is in the process of applying for a construction permit, planning to be built with a six-month gap. P3 is expected to be completed in the second quarter of 2028, and P4 is scheduled for completion in the fourth quarter of the same year. After the P2 factory is completed in the second half of next year, an additional 1,000 operational personnel will be added, with the total number of employees expected to be between 9,000 and 10,000 when all four new factories in Phase II are completed and put into production.

According to South Korea's "Cultural Daily," Samsung Electronics' wafer fab in Taylor, Texas, is expected to enter trial operation around the end of this month, as orders for 2-nanometer chips from Tesla, Broadcom, Arm, and others continue to pour in, with pre-production capacity nearing full load. The plant has accumulated an investment of $37 billion since 2022, with plans to begin trial operation early next month and mass production next year, with an initial monthly capacity of about 50,000 wafers, close to TSMC's approximately 80,000 wafers.The report states that the Taylor plant will produce Tesla's next-generation artificial intelligence chip AI5, Broadcom's new generation communication chips, and Arm's smart device AI chips, among others. Samsung's 2-nanometer yield has increased from about 60% earlier this year to around 80% recently. The company sent personnel for process, equipment, and yield to the plant in June, and began installing equipment in July. At a recent earnings meeting, Samsung projected that this year's 2-nanometer order volume would more than double compared to last year, and stated that NVIDIA's inference chip Grok3 began mass production last month; Samsung also recently raised the foundry price for 4-nanometer chips by up to 15%.The second Taylor plant is scheduled to start construction by the end of this year and begin mass production in 2030. Samsung has requested major partners to complete the relevant production equipment safety certifications in advance, and some partners are considering sending dozens of personnel to the local area. At the same time, Intel issued about $20 billion in new shares last month and expanded investments in 2-nanometer level 18A and 1.4-nanometer level 14A, while Japan's Rapidus completed its 2-nanometer factory in Hokkaido last month and entered the wafer trial production stage.