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first_img TSMC accelerates its layout in CPO, and the industry is optimistic about forming a new Moore's Law

According to Taiwan's "Commercial Times" report on September 14, as the computing power of GPUs and ASICs continues to rise, traditional copper interconnects are gradually approaching the limits of power consumption and signal transmission. TSMC is accelerating its layout for co-packaged optics (CPO). The industry is optimistic that if CPO bandwidth continues to double every two years, it may form the "CPO Moore's Law" of the AI era. Industry analysis indicates that the upgrade of CPO bandwidth mainly has three paths: including increasing single-channel speed from 200G to over 400G, expanding the number of optical channels from 16 to 32, 64 or more, and introducing wavelength division multiplexing (WDM). By 2040, the theoretical value could reach about 128 times the current level, with long-term potential for development towards hundreds of T based on the current level of about 3.2T.TSMC's role in optical interconnects has extended from wafer foundry to system integration, gradually integrating computing, HBM memory, and high-speed I/O from 3DFabric, CoWoS, SoIC to silicon photonics and CPO. When high-speed electrical signals exceed 200G, signal attenuation increases after passing through longer copper paths such as ABF substrates, PCBs, and connectors, leading the industry to develop shorter copper paths and longer optical paths. In terms of packaging architecture, the optical engine is currently laid out on the substrate, and the next step is expected to place CPO in the intermediary layer, with future possibilities of using SoIC technology to achieve 3D vertical integration of photonic integrated circuits (PIC) and ASICs. Industry players indicate that CPO still needs to overcome challenges in packaging, optical coupling, and testing before mass production can be achieved.

first_img Micron grants the highest bonuses in history, and the Taiwan union states it will continue to push for strikes

Micron announced today that it will distribute 2026 fiscal year bonuses to over 60,000 employees worldwide to acknowledge the company's achievements this year, marking the highest bonuses in Micron's history. Taiwan is a key hub for Micron's global technology leadership, with approximately 15,000 employees and a cumulative investment of over NT$1.6 trillion.In Taiwan, the 2026 fiscal year bonuses include a NT$1 million cash bonus for each employee who joins before August 29, 2025, with subsequent hires receiving bonuses proportionate to their duration of employment; an annual performance bonus that can reach up to 500% of the basic target; and additional stock awards. Production line employees in Taiwan will receive total compensation equivalent to 35 to 68 months of salary. The cash compensation for Micron's employees in Taiwan for the 2026 fiscal year will start at NT$1.7 million; entry-level engineers will have an average cash compensation of NT$2.9 million, with an average total compensation of NT$3.4 million after including stock awards calculated at grant value. The annual performance adjustment stock awards will cover 100%.Regarding Micron's announcement without reaching a consensus with the union, the union stated after collecting member opinions: grassroots members demand institutional reform and equal negotiation, calling for a change in the IPP profit-sharing system to a 15% profit-sharing system, stating that one-time bonuses cannot resolve the issue, and expressing the hope to establish a calculation basis directly linked to the company's actual profits. If there is no response, the union will continue to move towards a strike. The Ministry of Labor stated that it has fully grasped the relevant information and is maintaining close contact with the Taoyuan City Government, the Central Taiwan Science Park Administration, and the Taichung City Government.
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