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first_img South Korean media: China's semiconductor industry is being promoted by a team system involving government, banks, and enterprises

According to South Korea's "JoongAng Ilbo," China's semiconductor industry is organized through collaboration among the central government, local governments, state-owned financial institutions, and enterprises, forming a system for fundraising, factory construction, and infrastructure support. The China National Integrated Circuit Industry Investment Fund has a first phase of 138.7 billion RMB, a second phase of 204 billion RMB, and a third phase of 344 billion RMB, totaling 686.7 billion RMB, with investments in companies such as SMIC, Hua Hong Semiconductor, and Yangtze Memory Technologies.Changxin Memory, established for 10 years, has risen to fourth in global DRAM market share, with a net loss of 21.13 billion RMB over the past three years, while R&D and equipment investments during the same period reached 185.2 billion RMB, with Hefei's state-owned capital providing about 80% of the funding for early projects. South Korea's Samsung Electronics and SK Hynix are responsible for investments, employment, technology development, and support for partners. The South Korean government plans to guide 622 trillion KRW in private investment by 2047 and provide 17 trillion KRW in low-interest loans and 1.1 trillion KRW in semiconductor ecosystem funds, but most of the burden will fall on enterprises.Park Kyung-soo, Executive Vice President of the Korea Semiconductor Industry Association: The semiconductor industry will fall behind in the next upturn if investment stops; even during downturns, R&D, equipment investment, and orders for materials and components must be maintained, requiring long-term policy, financial, and tax support. China is catching up with a national-level support system, and South Korea also needs a response system involving the government, political circles, financial institutions, and enterprises to act together.

first_img TSMC accelerates its layout in CPO, and the industry is optimistic about forming a new Moore's Law

According to Taiwan's "Commercial Times" report on September 14, as the computing power of GPUs and ASICs continues to rise, traditional copper interconnects are gradually approaching the limits of power consumption and signal transmission. TSMC is accelerating its layout for co-packaged optics (CPO). The industry is optimistic that if CPO bandwidth continues to double every two years, it may form the "CPO Moore's Law" of the AI era. Industry analysis indicates that the upgrade of CPO bandwidth mainly has three paths: including increasing single-channel speed from 200G to over 400G, expanding the number of optical channels from 16 to 32, 64 or more, and introducing wavelength division multiplexing (WDM). By 2040, the theoretical value could reach about 128 times the current level, with long-term potential for development towards hundreds of T based on the current level of about 3.2T.TSMC's role in optical interconnects has extended from wafer foundry to system integration, gradually integrating computing, HBM memory, and high-speed I/O from 3DFabric, CoWoS, SoIC to silicon photonics and CPO. When high-speed electrical signals exceed 200G, signal attenuation increases after passing through longer copper paths such as ABF substrates, PCBs, and connectors, leading the industry to develop shorter copper paths and longer optical paths. In terms of packaging architecture, the optical engine is currently laid out on the substrate, and the next step is expected to place CPO in the intermediary layer, with future possibilities of using SoIC technology to achieve 3D vertical integration of photonic integrated circuits (PIC) and ASICs. Industry players indicate that CPO still needs to overcome challenges in packaging, optical coupling, and testing before mass production can be achieved.
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