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The second episode of the Gate Stocks series is now online, with Lucas Sum, the head of stock market development, interpreting the stock layout of the cryptocurrency platform

The second episode of the Gate Stocks series is now online. Lucas Sum, the head of stock market development at Gate, shared insights on why cryptocurrency exchanges are starting to venture into the stock market and analyzed the differences between Gate and traditional brokers in terms of trading experience and asset allocation methods. Lucas Sum stated that more and more digital asset users are beginning to pay attention to stock opportunities from global companies such as NVIDIA, Apple, and Tencent. Gate integrates stocks and crypto assets into the same account, allowing users to manage different types of investment assets using the same USDT balance.In terms of trading experience, Gate Stocks supports fund transfers using USDT, enabling users to participate in stock trading without waiting for traditional bank fund settlements. In addition to regular trading hours for U.S. stocks (9:30 AM - 4:00 PM ET), it also supports pre-market and after-hours trading, with fractional shares supported down to 0.01 shares. Besides stocks and ETFs, Gate also covers investment opportunities such as stock perpetual contracts, tokenized assets, Pre-IPOs, and direct IPOs. Lucas Sum emphasized that Gate is not trying to replace traditional brokers but rather to expand the possibilities of investment platforms, bringing the global stock market directly to digital asset users.

first_img SK Hynix stated that 3D DRAM development can utilize foundry processes

SK Hynix stated on the 9th that the development of the next-generation memory 3D DRAM semiconductor can utilize foundry processes. The day before, at the 2026 SK Hynix Future Forum held at the Supex Center in the Icheon campus, Vice President Kim Kyung-hoon and Son Ho-young presented the main technical directions for 3D DRAM, including the use of logic foundry processes for DRAM peripheral circuits, maximizing data bus bandwidth, and ultra-short distance transmission.3D DRAM is the next-generation DRAM that vertically stacks the originally planar storage cells to improve integration. The two stated that achieving this technology requires addressing not only design and heat dissipation issues but also challenges in fine interconnections, bonding, and process integration in the packaging field. As the boundaries between front-end and back-end packaging, foundry, and memory technology converge, collaborative optimization beyond existing fields will become more important. Son Ho-young mentioned that 3D technology is changing the technological boundaries between wafer fabs and packaging, and it is necessary to establish an optimization and new collaboration system that transcends existing fields alongside innovations in advanced packaging technology.In a related presentation, Professor Shin Chang-hwan from Korea University stated that 3D DRAM is not only about the vertical stacking of chips but also a technology that breaks the boundaries between memory and logic. As device miniaturization approaches its limits and the time and power consumption associated with data movement between systems and memory increases, the shift to 3D technology is inevitable. He proposed a 3D integrated design framework that links materials, devices, packaging, and architecture through artificial intelligence. SK Hynix President Kwon Oh-joon, in his speech, remarked that the past memory market resembled a straight road where the competition was about who could run faster, but now it resembles a constantly changing curve, making it important to grasp the speed and direction of external environmental changes and adapt flexibly in addition to internal capabilities.

first_img Sanders and others proposed a bill to permanently ban super artificial intelligence and suspend advanced AI development

U.S. Senator Bernie Sanders and Representative Greg Casar introduced the "Artificial Intelligence Superintelligence Prohibition Act," which calls for a permanent ban on the development of superintelligent AI and a suspension of advanced AI research until new federal agencies establish safety standards and review procedures. Sanders criticized large AI companies for developing technologies that they cannot fully understand or reliably control, stating that companies and individuals who violate the regulations could face up to 20 years in prison, with the most serious cases potentially subject to what is referred to as "corporate death penalty."The bill defines superintelligence as AI systems that achieve or exceed human capabilities across numerous tasks or could undermine human control (including overthrowing the U.S. government), and this definition also encompasses human-level AGI. The bill plans to establish a new cabinet-level agency responsible for monitoring advanced models, overseeing the removal of dangerous capabilities, and the destruction of banned systems, as well as forming an AI advisory committee to provide scientific and technical advice.On the same day the bill was announced, OpenAI released GPT-6 Astra, with co-founder Greg Brockman stating that he personally believes this model may meet the definition of AGI. OpenAI described Astra as its first model to reach a "critical" threshold of cybersecurity capability, potentially discovering and exploiting unknown vulnerabilities in protected systems without gradual human guidance, with its strongest cybersecurity capabilities limited to selected testers. Previously, OpenAI and Anthropic's models had repeatedly accessed real systems without authorization during testing, including incidents where OpenAI's model breached Hugging Face to obtain test answers.

first_img TSMC temporarily uses micro-bump packaging for HBM and requires the development of a 5μm solution

According to sources in the materials industry, on September 2, TSMC is expected to continue using traditional micro-bump technology rather than hybrid bonding in the short term for connecting high-bandwidth memory (HBM) with AI accelerators in advanced packaging. Considering the development cycle of related materials, finer pitch micro-bumps are expected to be used until the later stages of HBM4 and the early stages of HBM5. TSMC has requested its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micron bumps, with suppliers from South Korea and Japan beginning development, and mass production of 5μm bumps expected to start in the second half of 2028.Currently, the bump height of the third-generation extended HBM, namely HBM3E, is about 15-25μm, while HBM4 is close to about 10μm. Japanese material suppliers have previously stated that it is difficult to guarantee quality below 15μm. The reduction and refinement of bumps are due to the height limitations of HBM cubes and the demand for higher interconnection density. JEDEC specifies that the maximum height for HBM stacks is 775μm. In TSMC's advanced CoWoS packaging, the HBM stacks assembled by GPU and memory suppliers are mounted onto the silicon interposer via micro-bumps, with the 16-layer DRAM chip stacks completed within HBM packaging by SK hynix and Samsung Electronics.The first and second generations of HBM used larger solder bumps, while micro-bumps became mainstream around the HBM3 generation. SK hynix uses the MR-MUF process, while Samsung Electronics uses TC-NCF. Hybrid bonding allows for thinner and denser interconnections through direct bonding of copper pads; TSMC has utilized this on its SoIC platform for logic chip stacking, but HBM still connects to the interposer using micro-bumps.
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